US 12,446,234 B2
Resistive memory device and manufacturing method of the resistive memory device
In Ku Kang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 6, 2022, as Appl. No. 17/833,647.
Claims priority of application No. 10-2022-0009493 (KR), filed on Jan. 21, 2022.
Prior Publication US 2023/0240084 A1, Jul. 27, 2023
Int. Cl. H01L 27/24 (2006.01); G11C 13/00 (2006.01); H01L 45/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/84 (2023.02) [G11C 13/0002 (2013.01); H10B 63/34 (2023.02); H10N 70/011 (2023.02); H10N 70/063 (2023.02); H10N 70/8265 (2023.02); H10N 70/24 (2023.02); H10N 70/8833 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A method of manufacturing a resistive memory device, the method comprising:
forming a stack structure in which a plurality of first material layers and a plurality of second material layers are alternately stacked on each other;
forming a hole that penetrates the stack structure through the plurality of first material layers and the plurality of second material layers;
forming an uneven sidewall of the hole by forming an insulating pattern on a sidewall of each first material layer of the first material layers, which is exposed through the hole;
forming a gate insulating layer and a channel layer along the uneven sidewall of the hole, wherein the channel layer includes convex regions, in relation to a central portion of the hole, and concave regions, in relation to the central portion of the hole, between the convex regions; and
forming variable resistance layers on the concave regions of the channel layer.