US 12,446,233 B2
Variable resistance memory device
Song Yi Kim, Yongin-si (KR); and Junghyun Cho, Anyang-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 2, 2021, as Appl. No. 17/540,298.
Claims priority of application No. 10-2021-0023837 (KR), filed on Feb. 23, 2021.
Prior Publication US 2022/0271091 A1, Aug. 25, 2022
Int. Cl. H10B 63/00 (2023.01)
CPC H10B 63/84 (2023.02) 19 Claims
OG exemplary drawing
 
1. A variable resistance memory device, comprising:
a substrate;
a memory cell structure on the substrate, the memory cell structure including:
conductive layers, each of the conductive layers including conductive lines spaced apart from each other in a direction parallel to a top surface of the substrate, and memory cell arrays, the memory cell arrays and the conductive layers being alternatingly stacked in a first direction perpendicular to the top surface of the substrate;
a first peripheral circuit layer between the substrate and the memory cell structure, the first peripheral circuit layer including first transistors that constitute row and column decoders and first interconnection patterns extending vertically, the first transistors are connected to corresponding ones of the first interconnection patterns; and
a second peripheral circuit layer between the first peripheral circuit layer and the memory cell structure, the second peripheral circuit layer including second transistors that constitute row and column decoders and second interconnection patterns extending vertically with a first group of the second interconnection patterns connecting to corresponding ones of the first interconnection patterns and a second group of the second interconnection patterns connected to corresponding ones of the second transistors, and the second transistors including core transistors that are connected to corresponding ones of the conductive lines.