	US 12,446,231 B1
	Method of integrating a capacitor including a non-linear polar material with a transistor through wafer bonding
Mauricio Manfrini, Heverlee (BE); Noriyuki Sato, Hillsboro, OR (US); James David Clarkson, El Sobrante, CA (US); Abel Fernandez, Berkeley, CA (US); Somilkumar J. Rathi, San Jose, CA (US); Niloy Mukherjee, San Ramon, CA (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on May 31, 2023, as Appl. No. 18/326,433.
Application 18/326,433 is a continuation of application No. 18/167,816, filed on Feb. 10, 2023, granted, now 11,765,908.
Int. Cl. H10B 53/30 (2023.01)

CPC H10B 53/30 (2023.02)

22 Claims

1. A method of fabricating a device, the method comprising:

forming a multi-layer stack above a first substrate, the multi-layer stack comprises a non-linear polar dielectric material having a form ABO_X, wherein A and B are two different cations, and wherein x is 1, 2, or 3;

patterning the multi-layer stack to form a capacitor;

forming a first conductive structure on the capacitor;

forming a transistor above a second substrate;

forming a second conductive structure above the transistor, wherein the second conductive structure is coupled with a terminal of the transistor; and

bonding the first conductive structure with the second conductive structure.