US 12,446,230 B2
Ferroelectric memory device and memory array
Meng-Han Lin, Hsinchu (TW); Chia-En Huang, Hsinchu County (TW); and Sai-Hooi Yeong, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 5, 2023, as Appl. No. 18/178,529.
Claims priority of provisional application 63/417,676, filed on Oct. 19, 2022.
Prior Publication US 2024/0138153 A1, Apr. 25, 2024
Int. Cl. H10B 51/30 (2023.01); H10B 12/00 (2023.01); H10B 51/20 (2023.01); H10D 64/27 (2025.01)
CPC H10B 51/30 (2023.02) [H10B 12/20 (2023.02); H10B 12/30 (2023.02); H10B 12/34 (2023.02); H10B 51/20 (2023.02); H10D 64/512 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A ferroelectric memory device, comprising:
a word line;
a pair of source/drain electrodes, disposed at opposite sides of the word line, and elevated from the word line;
a channel layer, having a bottom planar portion and wall portions, wherein the bottom planar portion extends along a top surface of the word line, and opposite ends of the bottom planar portion are connected to sidewalls of the source/drain electrodes through opposite ones of the wall portions;
a work function layer, electrically connected to the word line, and extending along the bottom planar portion and the wall portions of the channel layer; and
a ferroelectric layer, separating the channel layer from the work function layer.