| CPC H10B 51/30 (2023.02) [H10B 51/20 (2023.02)] | 25 Claims |
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1. A semiconductor device comprising:
a substrate;
a bit line and a source line extending in a vertical direction that is substantially perpendicular to a surface of the substrate;
a semiconductor layer disposed between the source line and the bit line on a plane that is substantially parallel to the surface of the substrate;
a non-ferroelectric layer pattern disposed on the semiconductor layer;
a floating electrode layer pattern disposed on the non-ferroelectric layer pattern;
a ferroelectric layer pattern disposed on the floating electrode layer pattern; and
a word line disposed on the ferroelectric layer pattern,
wherein an overlap area between the floating electrode layer pattern and the non-ferroelectric layer pattern in the vertical direction is greater than an overlap area between the ferroelectric layer pattern and the word line in the vertical direction.
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