| CPC H10B 51/20 (2023.02) [G11C 16/0483 (2013.01); H01L 23/5283 (2013.01); H10B 51/10 (2023.02); H10B 51/50 (2023.02); H10D 84/0149 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A method for forming a three-dimensional (3D) memory array, comprising steps of:
depositing multiple isolation layers and multiple sacrificial layers that are alternately stacked in a Z-axis direction on a substrate to form a stack feature;
forming a plurality of trenches in the stack feature;
replacing the sacrificial layers with metal while the trenches remain to form a plurality of word lines that extend in a Y-axis direction;
conformally forming a gate dielectric layer and a channel layer in the trenches; and
forming multiple bit lines and multiple source lines that extend in the Z-axis direction in the trenches, the bit lines and the source lines cooperating with the word lines, the gate dielectric layer and the channel layer to form a plurality of memory cells that are distributed in multiple columns extending in the Y-axis direction and equidistantly arranged in an X-axis direction; and
forming a plurality of first bit-line connection wires that extend in the X-axis direction and that are arranged in the Y-axis direction, and a plurality of second bit-line connection wires that extend in the X-axis direction and that are arranged in the Y-axis direction, wherein the second bit-line connection wires are spaced apart from the first bit-line connection wires in the X-axis direction, and are electrically isolated from the first bit-line connection wires;
wherein:
the X-axis direction, the Y-axis direction and the Z-axis direction are transverse to each other;
each of the memory cells includes a first electrode, a second electrode and a gate electrode;
in each of the columns of the memory cells, the memory cells are distributed in multiple layers that are arranged in the Z-axis direction;
each of the bit lines interconnects the first electrodes of some of the memory cells aligned in the Z-axis direction;
each of the source lines interconnects the second electrodes of some of the memory cells aligned in the Z-axis direction;
each of the word lines interconnects the gate electrodes of some of the memory cells aligned in the Y-axis direction;
each of the first bit-line connection wires interconnects some of the bit lines that are aligned in the X-axis direction;
each of the second bit-line connection wires interconnects some of the bit lines that are aligned in the X-axis direction, and
wherein the first bit-line connection wires interconnect a first group of the bit lines, the second bit-line connection wires interconnect a second group of the bit lines, and one of the columns of the memory cells is disposed between the first group of the bit lines and the second group of the bit lines.
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