US 12,446,226 B2
Memory device and method of manufacturing the same
Jae Taek Kim, Icheon-si (KR); and Hye Yeong Jung, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 17, 2022, as Appl. No. 17/697,221.
Claims priority of application No. 10-2021-0126340 (KR), filed on Sep. 24, 2021.
Prior Publication US 2023/0094910 A1, Mar. 30, 2023
Int. Cl. H10B 43/40 (2023.01); H10B 41/41 (2023.01)
CPC H10B 43/40 (2023.02) [H10B 41/41 (2023.02)] 10 Claims
OG exemplary drawing
 
1. A memory device comprising:
a source layer over which a cell region and a peripheral circuit region are defined;
memory blocks formed on the source layer in the cell region;
a slit formed between the memory blocks;
a resistor formed in the source layer in the peripheral circuit region;
contacts formed on the resistor; and
metal lines formed on the contacts and connected to a peripheral circuit.