US 12,446,224 B2
Semiconductor memory device and manufacturing method of the semiconductor memory device
Kang Sik Choi, Seongnam-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 13, 2023, as Appl. No. 18/507,505.
Application 18/507,505 is a continuation of application No. 17/572,154, filed on Jan. 10, 2022, granted, now 11,856,777.
Application 17/572,154 is a continuation of application No. 16/908,162, filed on Jun. 22, 2020, granted, now 11,257,843, issued on Feb. 22, 2022.
Claims priority of application No. 10-2019-0138568 (KR), filed on Nov. 1, 2019.
Prior Publication US 2024/0081066 A1, Mar. 7, 2024
Int. Cl. H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a lower structure including transistors and interconnection structures respectively connected to the transistors;
a gate stack structure disposed over a portion of the lower structure;
a first semiconductor pattern disposed between the lower structure and the gate stack structure, wherein the gate stack structure includes a cell array region over the first semiconductor pattern and a contact region protruding farther laterally than the first semiconductor pattern from the cell array region;
a second semiconductor pattern disposed between the lower structure and the contact region of the gate stack structure;
a lower contact plug disposed between the second semiconductor pattern and a corresponding interconnection structure, among the interconnection structures;
a contact plug passing through the contact region of the gate stack structure and the second semiconductor pattern to be in contact with the lower contact plug; and
an insulating layer interposed between the contact plug and the gate stack structure and extending between the contact plug and the second semiconductor pattern.