| CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02)] | 19 Claims |
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1. A vertical non-volatile memory device comprising:
a memory stack structure including gate lines and interlayer insulating layers alternately stacked in a stacking direction and including a channel hole that is in the gate lines and the interlayer insulating layers and extends in the stacking direction;
a channel layer in the channel hole of the memory stack structure and extending in the stacking direction; and
an information storage structure including a composite blocking insulating layer, a charge storage layer, and a tunneling insulating layer sequentially arranged in a horizontal direction from the gate lines to the channel layer,
wherein the composite blocking insulating layer includes a first metal oxide having a higher dielectric constant than silicon oxide,
wherein the composite blocking insulating layer comprises a plurality of blocking insulating layers arranged in a descending order of oxidation density in the horizontal direction from the gate lines to the channel layer,
wherein a first one of the plurality of blocking insulating layers comprises portions extending on first, second, third, and fourth surfaces of the gate lines, respectively,
wherein the gate lines each comprise a single metal layer, and
wherein the first one of the plurality of blocking insulating layers comprises an insulator that directly contacts the first, second, third, and fourth surfaces of the gate lines.
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