| CPC H10B 43/27 (2023.02) [H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02)] | 18 Claims |
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1. A semiconductor memory device, comprising:
a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate;
semiconductor patterns that are respectively disposed between vertically adjacent word lines of the word lines;
a bit line that vertically extends from the semiconductor substrate and contacts the semiconductor patterns;
a capping insulating pattern disposed between the bit line and the word lines and covering side surfaces of the interlayer dielectric patterns; and
memory elements that are respectively disposed between vertically adjacent interlayer dielectric patterns of the interlayer dielectric patterns,
wherein each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions, wherein lateral ends of the capping insulating pattern are aligned with lateral ends of the first source/drain region,
wherein the semiconductor memory device further comprises a gate insulating layer interposed between the channel region and the word lines,
wherein the gate insulating layer directly contacts a side surface of the capping insulating pattern and does not directly contact the first source/drain region, and
wherein a largest width of the first source/drain region is greater than a width of the channel region.
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