US 12,446,218 B2
Memory cell with contiguous P-well and N-well structures
Roberto Bregoli, Offlaga (IT); Alessandro Ferretti, Villanuova Sul Clisi (IT); and Federica Rosa, Corsico (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Mar. 17, 2023, as Appl. No. 18/185,575.
Claims priority of application No. 102022000006035 (IT), filed on Mar. 28, 2022.
Prior Publication US 2023/0328979 A1, Oct. 12, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); H10B 41/35 (2023.01); H10B 41/70 (2023.01)
CPC H10B 41/70 (2023.02) [G11C 16/045 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); H10B 41/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory cell, comprising:
a body;
a first well of a first conductivity type in the body;
a second well of a second conductivity type in the body, the first and second wells being arranged adjacent and contiguous to each other, wherein the first conductivity type is P-type and the second conductivity type is N-type;
a first conduction region, a second conduction region and a third conduction region in the first well, the first, second, and third conduction regions being of the second conductivity type;
a control gate region of the second conductivity type in the second well, the control gate region being a single implanted region;
a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor; and
a floating gate region having a programming portion overlying the first well and a capacitive portion overlying the second well, the floating gate region forming, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element, wherein the non-volatile memory cell is configured to be programmed by channel hot electron injection effect at the storage transistor.