| CPC H10B 41/27 (2023.02) [G11C 5/063 (2013.01); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02)] | 20 Claims |

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1. A three-dimensional memory device, comprising:
an interconnect structure; and
a first deck formed over the interconnect structure in a first direction, the first deck including a first stack and a first channel structure, wherein:
the first stack includes alternated first insulating layers and first word line layers in the first direction,
the first channel structure extends through the first stack in the first direction and includes a first channel dielectric region and a first channel layer,
the first channel layer includes a first portion formed along the first channel dielectric region, a third portion formed in the interconnect structure, and a second portion between the first portion and the third portion in the first direction,
the first channel dielectric region is formed between the first stack and the first portion of the first channel layer in a second direction intersecting the first direction, disposed over a top surface of the interconnect structure, and
the second portion protrudes toward the first insulating layers relative to the third portion in the second direction.
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