US 12,446,216 B2
Memory device
Chien Hui Huang, Tainan (TW); Kao-Cheng Lin, Taipei (TW); Wei Min Chan, New Taipei (TW); Shang Lin Wu, Hsinchu County (TW); Chia-Chi Hung, Hsinchu (TW); Wei-Cheng Wu, Hsinchu (TW); Chia-Che Chung, Hsinchu (TW); Pei-Yuan Li, New Taipei (TW); Chien-Chen Lin, Kaohsiung (TW); Yung-Ning Tu, Changhua County (TW); and Yen Lin Chung, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 11, 2023, as Appl. No. 18/350,365.
Prior Publication US 2025/0024671 A1, Jan. 16, 2025
Int. Cl. G11C 17/00 (2006.01); G11C 5/06 (2006.01); G11C 11/56 (2006.01); H10B 20/00 (2023.01)
CPC H10B 20/50 (2023.02) [G11C 5/063 (2013.01); G11C 11/5692 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first memory cell comprising:
a first transistor; and
a second transistor coupled to the first transistor in parallel, wherein gates of the first transistor and the second transistor are coupled to each other,
wherein an active area of the first transistor and an active area of the second transistor extend in a first direction and overlap with each other in a layout view, and the gates of the first transistor and the second transistor extend in a second direction to pass different layers and the active area of the first and second transistors, the second direction being different from the first direction, wherein types of the first transistor and the second transistor are a same.