US 12,446,214 B2
Semiconductor structure
Jianfeng Xiao, Hefei (CN); and Xiaojie Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 5, 2023, as Appl. No. 18/150,245.
Application 18/150,245 is a continuation of application No. PCT/CN2022/112232, filed on Aug. 12, 2022.
Claims priority of application No. 202210714285.X (CN), filed on Jun. 22, 2022.
Prior Publication US 2023/0422489 A1, Dec. 28, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/488 (2023.02) [H10B 12/482 (2023.02); H10B 12/50 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a plurality of word lines extending along a first direction and arranged at intervals along a third direction;
a plurality of semiconductor channels extending along a second direction and arranged at intervals along the third direction, wherein the word line surrounds the semiconductor channel along the third direction, and the first direction, the second direction, and the third direction intersect one another;
a stepped structure comprising a plurality of steps, wherein the step is in contact with and connected to the word line, a height of a top surface of any one of the steps is different from a height of a top surface of another one of the steps along the third direction, the steps are arranged in an array along the first direction and the second direction, and adjacent ones of the steps are electrically insulated from each other; and
a plurality of contact structures, wherein the contact structure is in contact with and connected to the step, and any two of the contact structures are spaced from each other.