US 12,446,212 B2
Semiconductor structure, method for manufacturing same and memory
Guangsu Shao, Hefei (CN); Deyuan Xiao, Hefei (CN); Yunsong Qiu, Hefei (CN); Yi Jiang, Hefei (CN); and Xingsong Su, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 17, 2023, as Appl. No. 18/171,284.
Claims priority of application No. 202210939226.2 (CN), filed on Aug. 5, 2022.
Prior Publication US 2024/0049453 A1, Feb. 8, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/02 (2023.02); H10B 12/488 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a plurality of mutually parallel first trenches extending along a first direction in the substrate and first isolation structures filling the first trenches, wherein the first direction is parallel to a surface of the substrate;
forming a plurality of mutually parallel second trenches extending along a second direction in the substrate and in the first isolation structures, wherein the first trenches and the second trenches divide the substrate to form a plurality of active pillars, the second direction is parallel to the surface of the substrate and perpendicular to the first direction, and a depth of the second trenches is less than a depth of the first trenches;
forming second isolation structures alternately arranged with the first isolation structures along the second direction at bottoms of the second trenches, wherein top surfaces of the second isolation structures are lower than bottom surfaces of the second trenches located in the first isolation structures;
forming a plurality of mutually parallel bit line structures extending along the first direction on the second isolation structures, wherein each of the bit line structures penetrates a plurality of active pillars along the first direction; and
forming a plurality of mutually parallel word line structures extending along the second direction above the bit line structures.