US 12,446,210 B2
Memory cell and method
Meng-Han Lin, Hsinchu (TW); Han-Jong Chia, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); Chi On Chui, Hsinchu (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 18, 2022, as Appl. No. 17/747,694.
Application 17/747,694 is a continuation of application No. 16/901,885, filed on Jun. 15, 2020, granted, now 11,342,334.
Prior Publication US 2022/0285349 A1, Sep. 8, 2022
Int. Cl. H10B 12/00 (2023.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01); H10D 30/67 (2025.01)
CPC H10B 12/33 (2023.02) [H10B 12/036 (2023.02); H10B 12/05 (2023.02); H10D 1/042 (2025.01); H10D 1/714 (2025.01); H10D 30/6735 (2025.01)] 20 Claims
OG exemplary drawing
 
8. A semiconductor device comprising:
a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a first dielectric layer, a second dielectric layer, a third dielectric layer, a fourth dielectric layer, a first semiconductor layer, and a first metal layer, wherein the first semiconductor layer comprises a channel region, a first source/drain region, and a second source/drain region;
a gate structure on the channel region; and
a capacitor in contact with the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, the first semiconductor layer, and the first metal layer, wherein the capacitor extends beneath the gate structure from a first side of the gate structure to a second side of the gate structure opposite the first side.