US 12,446,209 B2
Semiconductor structure and method for fabricating the same
Dong Yan, Hefei (CN); Zijie Wang, Hefei (CN); Jun Wei, Hefei (CN); and Wei Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 4, 2023, as Appl. No. 18/149,671.
Claims priority of application No. 202210727229.X (CN), filed on Jun. 24, 2022.
Prior Publication US 2023/0422480 A1, Dec. 28, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/315 (2023.02) [H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10B 12/482 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming, in the substrate, a plurality of active pillars arranged at intervals and isolation layers configured to isolate the plurality of active pillars;
forming, in a given one of the plurality of active pillars and a given one of the isolation layers, a plurality of word line trenches extending along a first direction, each of the plurality of word line trenches being configured to communicate with the plurality of active pillars positioned in the same first direction, and each of the plurality of word line trenches comprising a first word line trench and a second word line trench spaced along a second direction; and
forming a first word line in the first word line trench and a second word line in the second word line trench, in the second direction, opposite surfaces of the first word line forming a first gate channel together with the given active pillar, opposite surfaces of the second word line forming a second gate channel together with the given active pillar, sum of a width of the first gate channel along the first direction and a width of the second gate channel along the first direction being greater than a perimeter of the given active pillar, and the first direction intersecting with the second direction.