US 12,446,208 B2
Multilevel wordline assembly for embedded DRAM
Juan G. Alzate-Vinasco, Tigard, OR (US); Travis W. LaJoie, Forest Grove, OR (US); Elliot N. Tan, Portland, OR (US); Kimberly Pierce, Beaverton, OR (US); Shem Ogadhoh, West Linn, OR (US); Abhishek A. Sharma, Portland, OR (US); Bernhard Sell, Portland, OR (US); Pei-Hua Wang, Hillsboro, OR (US); and Chieh-Jen Ku, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,954.
Prior Publication US 2022/0415897 A1, Dec. 29, 2022
Int. Cl. H10D 30/67 (2025.01); H10B 12/00 (2023.01); H10D 30/01 (2025.01)
CPC H10B 12/315 (2023.02) [H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10D 30/031 (2025.01); H10D 30/6728 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A device structure comprising:
a first interconnect line along a longitudinal direction, wherein the first interconnect line is within a first metallization level;
a second interconnect line parallel to the first interconnect line, wherein the second interconnect line is within a second metallization level;
a first transistor adjacent to a second transistor, the second transistor laterally separated from the first transistor, wherein a gate of the first transistor is coupled to the first interconnect line and wherein a gate of the second transistor is coupled to the second interconnect line;
a via between the first interconnect line and the gate of the first transistor;
a first capacitor and a second capacitor on a side of the first and second transistors opposite the first and second metallization levels, wherein the first capacitor is coupled to a first terminal of the first transistor and the second capacitor is coupled to a first terminal of the second transistor; and
a third interconnect line coupling a second terminal of the first transistor with a second terminal of the second transistor, the third interconnect line extending along a first direction orthogonal to the longitudinal direction,
wherein:
the via is a first via comprising a first end intersecting the first interconnect line and a second end intersecting the gate of the first transistor;
the device structure further comprises a second via comprising a first end intersecting the second interconnect line and a second end intersecting the gate of the second transistor;
the first interconnect line is separated from the second interconnect line by a first vertical thickness measured along a second direction orthogonal to the first and the longitudinal directions;
the second interconnect line has a second vertical thickness measured along the second direction;
the second via has a third vertical thickness measured along the second direction;
the first via has a fourth vertical thickness measured along the second direction and wherein the fourth vertical thickness is substantially equal to a sum of the first, the second and the third vertical thicknesses.