US 12,446,207 B2
Semiconductor device having bottom bit line and narrow channel, and forming method thereof
Guangsu Shao, Hefei (CN); Deyuan Xiao, Hefei (CN); Yunsong Qiu, Hefei (CN); and Youming Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jun. 8, 2022, as Appl. No. 17/805,977.
Application 17/805,977 is a continuation of application No. PCT/CN2022/085761, filed on Apr. 8, 2022.
Prior Publication US 2023/0301064 A1, Sep. 21, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/312 (2023.02) [H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10B 12/488 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A forming method of a semiconductor device, comprising:
providing a substrate;
etching the substrate to form first recesses and second recesses located below the first recesses and communicating with the first recesses;
forming a bit line in the second recesses;
forming, at bottoms of the first recesses, an isolation layer covering the bit line;
enlarging an inner diameter of each of the first recesses above the isolation layer; and
forming a gate layer on a sidewall of each of the first recesses whose inner diameter is enlarged;
wherein forming first recesses and second recesses located below the first recesses and communicating with the first recesses comprises:
etching the substrate to form a plurality of first recesses arranged parallel to and spaced apart from each other along a first direction and an active pillar located between adjacent ones of the first recesses, wherein the first recesses extend along a direction perpendicular to a top surface of the substrate, and the first direction is a direction parallel to the top surface of the substrate; and
etching the substrate along the first recesses, and forming, below the first recesses, the second recesses communicating with the first recesses, wherein an inner diameter of each of the second recesses is greater than the inner diameter of the first recess located above and communicating with the each of the second recesses;
wherein a remaining part of the substrate between every two adjacent ones of the second recesses spaced apart from each other along the first direction forms a separation pillar;
and the forming a bit line in the second recesses comprises:
implanting doping elements into each of the separation pillars and a part of the substrate at a bottom of each of the second recesses to form a bit line contact layer distributed continuously in the second recesses arranged along the first direction; and
forming a bit line conductive layer filling each of the second recesses and covering the bit line contact layer to form the bit line comprising the bit line contact layer and the bit line conductive layer.