US 12,446,204 B2
SRAM with P-type access transistors and complementary field-effect transistor technology
Charles Augustine, Portland, OR (US); Seenivasan Subramaniam, Hillsboro, OR (US); Patrick Morrow, Portland, OR (US); and Muhammad M. Khellah, Tigard, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 3, 2022, as Appl. No. 17/686,241.
Prior Publication US 2023/0284427 A1, Sep. 7, 2023
Int. Cl. H10B 10/00 (2023.01); G11C 11/412 (2006.01); G11C 11/419 (2006.01)
CPC H10B 10/12 (2023.02) [G11C 11/412 (2013.01); G11C 11/419 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first n-type region comprising a first nMOS transistor and a first gate connector;
a second n-type region comprising a second nMOS transistor and a second gate connector;
a first p-type region below the first n-type region, the first p-type region comprising first and second pMOS transistors; and
a second p-type region below the second n-type region, the second p-type region comprising third and fourth pMOS transistors, wherein the first gate connector has an overlapping footprint with the first pMOS transistor.