US 12,446,199 B2
On-chip shielded device
Philipp Franz Freidl, Weurt (NL); Mustafa Acar, Eindhoven (NL); Antonius Hendrikus Jozef Kamphuis, Nijmegen (NL); Erik Daniel Björk, Sollentuna (SE); Konstantinos Giannakidis, Eindhoven (NL); Jan Willem Bergman, Veghel (NL); Rajesh Mandamparambil, Eindhoven (NL); and Paul Mattheijssen, Boxtel (NL)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., Eindhoven (NL)
Filed on Oct. 21, 2022, as Appl. No. 18/048,495.
Prior Publication US 2024/0138129 A1, Apr. 25, 2024
Prior Publication US 2024/0237316 A9, Jul. 11, 2024
Int. Cl. H05K 9/00 (2006.01); H01L 23/552 (2006.01)
CPC H05K 9/0032 (2013.01) [H01L 23/552 (2013.01); H05K 9/0088 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An on-chip shielded device, comprising:
a semiconductor material coupled to a passivation layer;
an electrical component formed within the semiconductor material and coupled to an input signal path and an output signal path;
a first shielding element positioned above the semiconductor material, the electrical component and the passivation layer; and
a second shielding element positioned above the semiconductor material, the electrical component, the passivation layer and the first shielding element;
wherein the first shielding element and the second shielding element each have a lateral dimension that only covers the semiconductor material.