US 12,446,153 B2
Circuit substrate and method for manufacturing the same
Motohiro Umehara, Yasu (JP); and Yoshinori Kubo, Omihachiman (JP)
Assigned to KYOCERA Corporation, Kyoto (JP)
Appl. No. 18/018,522
Filed by KYOCERA Corporation, Kyoto (JP)
PCT Filed Jul. 21, 2021, PCT No. PCT/JP2021/027274
§ 371(c)(1), (2) Date Jan. 27, 2023,
PCT Pub. No. WO2022/024907, PCT Pub. Date Feb. 3, 2022.
Claims priority of application No. 2020-128334 (JP), filed on Jul. 29, 2020.
Prior Publication US 2023/0300983 A1, Sep. 21, 2023
Int. Cl. H05K 1/11 (2006.01); H05K 3/42 (2006.01)
CPC H05K 1/115 (2013.01) [H05K 3/423 (2013.01); H05K 2201/09563 (2013.01); H05K 2203/0723 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A circuit substrate comprising:
an insulation substrate formed with a plurality of via holes passing through a first main surface and a second main surface, the first main surface and the second main surface being opposing main surfaces;
a second metal layer with which the plurality of via holes are filled; and
a third metal layer coating an entire surface of the second metal layer,
wherein the second metal layer is a plated metal, and the third metal layer is a plated metal,
wherein the third metal layer is denser and harder than the second metal layer, and
wherein an interface between the second metal layer and the third metal layer is located between the first main surface and the second main surface in the via hole, and the interface between the second metal layer and the third metal layer is a polished surface.