US 12,445,903 B2
Base station device, terminal device, communication method and communication system
Yoshiaki Ohta, Yokohama (JP); Takayoshi Ode, Yokohama (JP); and Yoshihiro Kawasaki, Kawasaki (JP)
Assigned to FUJITSU LIMITED, Kawasaki (JP)
Filed by FUJITSU LIMITED, Kawasaki (JP)
Filed on Feb. 18, 2025, as Appl. No. 19/055,880.
Application 19/055,880 is a continuation of application No. 17/231,149, filed on Apr. 15, 2021.
Application 17/231,149 is a continuation of application No. 16/460,379, filed on Jul. 2, 2019, granted, now 11,032,738, issued on Jun. 8, 2021.
Application 16/460,379 is a continuation of application No. 16/260,672, filed on Jan. 29, 2019, granted, now 10,397,828, issued on Aug. 27, 2019.
Application 16/260,672 is a continuation of application No. PCT/JP2018/014339, filed on Apr. 3, 2018.
Prior Publication US 2025/0193732 A1, Jun. 12, 2025
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 28/06 (2009.01); H04W 80/02 (2009.01); H04W 88/08 (2009.01)
CPC H04W 28/06 (2013.01) [H04W 80/02 (2013.01); H04W 88/08 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A transmitting device comprising:
a transmitter configured to transmit first data of a first type for a first logical channel, and to transmit second data of a second type for a second logical channel; and
processor circuitry configured to:
place, in a medium access control (MAC) layer, a first MAC header in front of a MAC service data unit (MSDU) including the second data, the second data being transferred to the MAC layer from a layer that is higher than the MAC layer, the first MAC header including a Reserve field (R-field) and a Logical Channel Identifier (LCID) field, the LCID field of the first MAC header which is placed in front of the MSDU being set to a first index which is selected from a plurality of indices, the first index indicating a first LCID value, the first LCID value being used for the second data in the MSDU, and
multiplex the first data and the second data, wherein information about a data length of the MSDU is omitted from the first MAC header and a Reserve bit (R bit) is set at bit one in a first octet in the first MAC header, the data length of the MSDU being fixed, and
wherein the processor circuitry is further configured to select the first MAC header from a plurality of MAC headers, the plurality of MAC headers including:
the first MAC header that includes the first octet, the R-field being located at the bit one of the first octet, and another R-field being located at bit two of the first octet, the LCID field being located from bit three to bit eight of the first octet, and
a second MAC header that includes:
a first octet which includes an R-field and an LCID field; and
a second octet which includes a Length field (L-field).