| CPC H04N 19/70 (2014.11) [H04N 19/172 (2014.11); H04N 19/82 (2014.11)] | 21 Claims |

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1. A video signal decoding device comprising:
a processor,
wherein the processor is configured to:
parse a first syntax element indicating whether information related to at least one sub-picture included in each picture is present,
parse a second syntax element indicating whether sub-picture ID mapping for the at least one sub-picture is signaled when the first syntax element indicates that the information related to the at least one sub-picture is present,
parse a third syntax element indicating whether the sub-picture ID mapping for the at least one sub-picture is signaled on a sequence parameter set (SPS) raw byte sequence payload (RBSP) syntax when the second syntax element indicates that the sub-picture ID mapping for the at least one sub-picture is signaled,
parse a fourth syntax element indicating whether the sub-picture ID mapping for the at least one sub-picture is signaled on a picture parameter set (PPS) RBSP syntax,
wherein when the third syntax element indicates that the sub-picture ID mapping for the at least one sub-picture is signaled on the SPS RBSP syntax, a sub-picture ID of a sub-picture among the at least one sub-picture is signaled on the SPS RBSP syntax, and
wherein when the second syntax element indicates that the sub-picture ID mapping for the at least one sub-picture is signaled and the third syntax element indicates that the sub-picture ID mapping for the at least one sub-picture is not signaled on the SPS RBSP syntax, the fourth syntax element indicates that the sub-picture ID mapping for the at least one sub-picture is signaled on the PPS RBSP syntax, and the sub-picture ID of the sub-picture among the at least one sub-picture is signaled on the PPS RBSP syntax.
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