| CPC H04N 19/65 (2014.11) [H04N 19/15 (2014.11); H04N 19/573 (2014.11); H04N 19/70 (2014.11); H04N 19/88 (2014.11); H04N 19/172 (2014.11); H04N 19/184 (2014.11)] | 20 Claims |

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1. A video decoder system comprising:
a buffer, implemented in memory, configured to receive encoded data in a bitstream for multiple pictures in a video sequence; and
a video decoder, implemented with one or more processing units and memory, configured to perform operations to decode the multiple pictures, wherein each of the multiple pictures is designated as being one of multiple picture types, the multiple picture types including (a) a first picture type indicating a broken link access (“BLA”) picture that is capable of being used as a random access point (“RAP”) picture and does not have any associated non-decodable leading pictures, but may have one or more associated decodable leading pictures, (b) a second picture type indicating a BLA picture that is capable of being used as a RAP picture but does not have any associated leading pictures, and (c) a third picture type indicating a random access decodable leading (“RADL”) picture, and wherein the operations include:
decoding a first picture among the multiple pictures, the first picture being designated as the first picture type; and
decoding a second picture among the multiple pictures, the second picture being designated as the third picture type.
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