US 12,445,542 B2
Configuring a switch for extracting packet header fields
Patrick Bosshart, Plano, TX (US)
Assigned to Barefoot Networks, Inc., Santa Clara, CA (US)
Filed by Barefoot Networks, Inc., Santa Clara, CA (US)
Filed on Jun. 21, 2023, as Appl. No. 18/212,546.
Application 18/212,546 is a continuation of application No. 17/570,994, filed on Jan. 7, 2022, abandoned.
Application 17/570,994 is a continuation of application No. 16/288,074, filed on Feb. 27, 2019, granted, now 11,245,778, issued on Feb. 8, 2022.
Application 16/288,074 is a continuation of application No. 15/729,593, filed on Oct. 10, 2017, granted, now 10,225,381, issued on Mar. 5, 2019.
Application 15/729,593 is a continuation of application No. 14/836,855, filed on Aug. 26, 2015, granted, now 9,826,071, issued on Nov. 21, 2017.
Prior Publication US 2023/0344922 A1, Oct. 26, 2023
Int. Cl. H04L 45/745 (2022.01); H04L 49/00 (2022.01); H04L 69/22 (2022.01)
CPC H04L 69/22 (2013.01) [H04L 49/3009 (2013.01)] 20 Claims
OG exemplary drawing
 
1. Integrated circuit for use in packet switching-related operations in a network, the integrated circuit being configurable to be used in a hardware switch in association with ternary content addressable memory (TCAM), the packet switching-related operations being programmable based upon configuration data to be received by the integrated circuit, the integrated circuit comprising:
an ingress pipeline to process packet data received by the integrated circuit;
a shared queuing system to queue the packet data processed by the ingress pipeline; and
an egress pipeline to obtain, from the shared queuing system, the packet data processed by the ingress pipeline, and also to further process the packet data processed by the ingress pipeline;
wherein:
the ingress pipeline comprises a configurable parser and configurable match-action stages;
the egress pipeline comprises at least one other stage;
the configurable parser is to be configured, in accordance with the configuration data, to parse packet header fields to generate multiple sets of header field data;
the multiple sets of header field data comprise (1) at least one set of header field data for use by at least one of the match-action stages and (2) at least one other set of header field data;
the at least one of the match-action stages is to perform actions associated with at least certain portions of the at least one set of header field data;
the at least one of the match-action stages is to determine the actions based upon matching, at least in part, of the at least one set of header field data with match table data;
the match action table data is configurable to comprise both (1) ternary content addressable table data to be stored in the TCAM and (2) exact match table data;
the actions and the match action table data are to be configured based upon the configuration data;
the actions are configurable to comprise packet header data modification and/or packet data port assignment;
the at least one other stage is to generate output packet data for output from the integrated circuit;
the at least one other stage is to generate the output packet data based upon modified packet header data generated by the at least one of the match-action stages;
the at least one other set of header field data is unavailable for match-action stage modification; and
the parser is configurable, based upon the configuration data, to store the at least one set of header field data, at least in part, in containers of different sizes.