US 12,445,524 B2
Methods and apparatus to share memory across distributed coherent edge computing system
Francesc Guim Bernat, Barcelona (ES); Karthik Kumar, Chandler, AZ (US); and Thomas Willhalm, Sandhausen (DE)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,040.
Prior Publication US 2022/0014588 A1, Jan. 13, 2022
Int. Cl. H04L 67/1097 (2022.01); G06F 12/0817 (2016.01); G06F 13/16 (2006.01); G06F 13/36 (2006.01)
CPC H04L 67/1097 (2013.01) [G06F 12/0828 (2013.01); G06F 13/1668 (2013.01); G06F 13/36 (2013.01); G06F 2212/621 (2013.01); G06F 2213/40 (2013.01)] 28 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one memory;
instructions in the apparatus; and
at least one processor circuit to execute the instructions to:
configure a compute express link (CXL) endpoint to facilitate communication, via a CXL interconnect, between a first Edge compute node including a first memory and a second Edge compute node including a second memory, the first Edge compute node and the second Edge compute node to form an Edge platform;
configure a coherent memory domain between the first memory and the second memory, the coherent memory domain including first memory addresses associated with first data from an Edge device that is to remain coherent across the Edge platform;
configure a coherency rule of the coherent memory domain, the coherency rule to define a level of coherency for the coherent memory domain;
configure at least one of the first Edge compute node or the second Edge compute node to be a home Edge compute node, main memory of the home Edge compute node to store the first data, the first memory addresses associated with the first data, and identifiers of the first Edge compute node and the second Edge compute node; and
snoop the CXL interconnect for second data at second memory addresses within the coherent memory domain, the second data permitted to be shared based on the coherency rule.