US 12,445,395 B2
Network interface device
Steven L. Pope, Cambridge (GB); Derek Roberts, Cambridge (GB); David J. Riddoch, Huntingdon (GB); and Dmitri Kitariev, Newport Beach, CA (US)
Assigned to Xilinx, Inc., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Jul. 18, 2022, as Appl. No. 17/867,646.
Application 17/867,646 is a continuation of application No. 16/870,814, filed on May 8, 2020, granted, now 11,394,664.
Application 16/870,814 is a continuation of application No. 16/226,453, filed on Dec. 19, 2018, granted, now 10,686,731, issued on Jun. 16, 2020.
Application 16/226,453 is a continuation in part of application No. 15/847,778, filed on Dec. 19, 2017, granted, now 10,686,872, issued on Jun. 16, 2020.
Prior Publication US 2023/0006945 A1, Jan. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 49/506 (2022.01); H04L 45/00 (2022.01); H04L 49/00 (2022.01); H04L 49/101 (2022.01); H04L 49/103 (2022.01); H04L 49/90 (2022.01); H04L 69/16 (2022.01)
CPC H04L 49/506 (2013.01) [H04L 45/66 (2013.01); H04L 49/101 (2013.01); H04L 49/103 (2013.01); H04L 49/30 (2013.01); H04L 49/9021 (2013.01); H04L 69/161 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A network interface device configured to interface between a network and a host device, the network interface device comprising:
first network interface device circuitry;
host interface circuitry;
host offload circuitry; and
interface circuitry coupled to: i) the first network interface device circuitry, ii) the host interface circuitry, and iii) the host offload circuitry, the interface circuitry comprising a plurality of hardware ports;
wherein the first network interface device circuitry has at least one port configured to be coupled to at least one respective port of the interface circuitry,
wherein the host interface circuitry is configured to interface to the host device, said host interface circuitry having at least one port configured to be coupled to respective port of the interface circuitry,
wherein the host offload circuitry is configured to perform an offload operation for the host device, said host offload circuitry having at least one port configured to be coupled to respective port of the interface circuitry, and
wherein the host offload circuitry comprises slices, each slice capable of being switched dynamically from processing received data to processing transmitted data.