US 12,445,330 B2
High-speed signaling systems with adaptable pre-emphasis and equalization
Jared L. Zerbe, Woodside, CA (US); Fred F. Chen, San Francisco, CA (US); Andrew Ho, San Jose, CA (US); Ramin Farjad-Rad, Los Altos, CA (US); John W. Poulton, Chapel Hill, NC (US); Kevin S. Donnelly, Los Altos, CA (US); Brian S. Leibowitz, San Francisco, CA (US); and Vladimir Stojanovic, Berkeley, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Oct. 15, 2021, as Appl. No. 17/503,085.
Application 17/503,085 is a continuation of application No. 16/256,882, filed on Jan. 24, 2019, granted, now 11,165,613.
Application 16/256,882 is a continuation of application No. 16/010,445, filed on Jun. 16, 2018, granted, now 10,205,614, issued on Feb. 12, 2019.
Application 16/010,445 is a continuation of application No. 15/652,059, filed on Jul. 17, 2017, granted, now 10,003,484, issued on Jun. 19, 2018.
Application 15/652,059 is a continuation of application No. 13/896,224, filed on May 16, 2013, granted, now 9,742,602, issued on Aug. 22, 2017.
Application 13/896,224 is a continuation of application No. 11/336,045, filed on Jan. 20, 2006, granted, now 9,137,063, issued on Sep. 15, 2015.
Claims priority of provisional application 60/686,754, filed on Jun. 1, 2005.
Claims priority of provisional application 60/645,823, filed on Jan. 20, 2005.
Prior Publication US 2022/0103405 A1, Mar. 31, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 27/01 (2006.01); H04L 1/00 (2006.01); H04L 7/033 (2006.01); H04L 25/03 (2006.01); H04L 25/497 (2006.01); H04W 52/20 (2009.01); H04L 7/00 (2006.01); H04L 25/02 (2006.01); H04W 52/22 (2009.01)
CPC H04L 27/01 (2013.01) [H04L 1/0026 (2013.01); H04L 7/0337 (2013.01); H04L 25/03057 (2013.01); H04L 25/03343 (2013.01); H04L 25/03885 (2013.01); H04L 25/497 (2013.01); H04W 52/20 (2013.01); H04L 7/0025 (2013.01); H04L 7/0087 (2013.01); H04L 25/0272 (2013.01); H04L 25/028 (2013.01); H04L 2025/03503 (2013.01); H04W 52/225 (2013.01); Y02D 30/70 (2020.08)] 20 Claims
OG exemplary drawing
 
1. A method of operating a first integrated circuit (IC), comprising:
transmitting, from the first IC to a second IC that is separate from the first IC, a digital bitstream;
receiving, at the first IC, a setting from the second IC based on an updated setting of a decision feedback equalizer (DFE) of the second IC, the updated setting generated by a control circuit on the second IC; and
wherein the updated setting is based on a measure of quality of the digital bit stream as received by the second IC.