US 12,445,312 B2
I/O circuit design for SRAM-based PUF generators
Jui-Che Tsai, Tainan (TW); Shih-Lien Linus Lu, Hsinchu (TW); Cheng Hung Lee, Hsinchu (TW); and Chia-En Huang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Mar. 12, 2024, as Appl. No. 18/602,593.
Application 18/602,593 is a continuation of application No. 17/222,806, filed on Apr. 5, 2021, granted, now 11,949,799.
Application 17/222,806 is a continuation of application No. 16/383,383, filed on Apr. 12, 2019, granted, now 10,972,292.
Claims priority of provisional application 62/752,929, filed on Oct. 30, 2018.
Prior Publication US 2024/0214226 A1, Jun. 27, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/32 (2006.01); G11C 7/06 (2006.01); G11C 11/4091 (2006.01); H04L 9/08 (2006.01)
CPC H04L 9/3278 (2013.01) [G11C 7/06 (2013.01); G11C 11/4091 (2013.01); H04L 9/0861 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A physical unclonable function (PUF) generator comprising:
a PUF cell array comprising a plurality of bit cells, and
at least one input/output (I/O) circuit each coupled to at least two columns of the PUF cell array, wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells of the plurality of bit cells, and based on the determined logical states, to generate a PUF signature,
wherein the at least one I/O circuit each comprises two cross-coupled invertors,
wherein a respective output of each of the two cross-coupled inverters is directly connected to a respective one of two first bit lines of the PUF cell array.