US 12,445,311 B2
Mitigating FPGA related risks
Dirk Koch, Berlin (DE); Ahmad-Reza Sadeghi, Darmstadt (DE); Jo Vliegen, Leuven (BE); Shaza Zeitouni, Darmstadt (DE); and Nele Mentens, Leuven (BE)
Assigned to Technische Universität Darmstadt, Darmstadt (DE); Dirk Koch, Berlin (DE); Katholieke Universiteit Leuven, Leuven (BE); and imee vzw, Leuven (BE)
Filed by Technische Universität Darmstadt, Darmstadt (DE); Dirk Koch, Berlin (DE); Katholieke Universiteit Leuven, Leuven (BE); and imec vzw, Leuven (BE)
Filed on Nov. 9, 2023, as Appl. No. 18/505,546.
Application 18/505,546 is a continuation of application No. PCT/EP2022/062476, filed on May 9, 2022.
Claims priority of application No. 21172917 (EP), filed on May 9, 2021.
Prior Publication US 2024/0073040 A1, Feb. 29, 2024
Int. Cl. H04L 9/32 (2006.01); G06F 21/51 (2013.01); G06F 21/76 (2013.01)
CPC H04L 9/3278 (2013.01) [G06F 21/51 (2013.01); G06F 21/76 (2013.01); G06F 2221/034 (2013.01)] 16 Claims
OG exemplary drawing
 
1. Computer-implemented method for operating a host computer that is communicatively coupled to a configuration computer via a communication network, and that is associated with a FPGA having a fabric area, the method being a method to configure the FPGA to execute a target array application, the method comprising:
the host computer forwarding identity information of the FPGA to the configuration computer, and the host computer receiving target configuration data from the configuration computer in encrypted form, wherein the encrypted form has been prepared by processing a response previously obtained by challenging the FPGA with a challenge;
receiving target configuration data ([TARGET_CONFIG]) from the configuration computer in encrypted form;
by a scanner module that is connected to the FPGA, decrypting the target configuration data and scanning the target configuration data for malicious code;
for malicious code being absent, writing the target configuration data to the fabric area of the FPGA, thereby configuring the FPGA accordingly, to enable execution of the target array application; and
confirming the integrity of the target array application on the FPGA by using the response in an auxiliary array application associated with the host computer, wherein the auxiliary array application causes the FPGA to transmit a proof value to the configuration computer.