US 12,445,235 B2
Electronic device for updating frame error rate of link and operation method of electronic device
Junsu Choi, Suwon-si (KR); Changmok Yang, Suwon-si (KR); Chounjong Nam, Suwon-si (KR); Sungbin Min, Suwon-si (KR); Mincheol Jeong, Suwon-si (KR); and Junyeop Jung, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 8, 2024, as Appl. No. 18/437,158.
Application 18/437,158 is a continuation of application No. PCT/KR2022/008082, filed on Jun. 8, 2022.
Claims priority of application No. 10-2021-0119768 (KR), filed on Sep. 8, 2021.
Prior Publication US 2024/0178949 A1, May 30, 2024
Int. Cl. H04L 1/18 (2023.01); H04L 1/00 (2006.01); H04L 1/20 (2006.01); H04L 43/16 (2022.01)
CPC H04L 1/203 (2013.01) [H04L 1/0013 (2013.01); H04L 43/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a communication circuit configured to transmit or receive data through a plurality of links established between an external electronic device and the electronic device;
a memory configured to store mapping data in which a data rate and a frame error rate for the plurality of links are mapped; and
a processor operatively connected to the communication circuit and the memory,
wherein the processor is configured to:
identify a link that has transmitted or received a number of packets smaller than a designated value among the plurality of links in response to a request for transmission of packets of a first type,
transmit or receive a plurality of packets of a second type through the identified link,
identify a frame error rate for the plurality of packets of the second type, and
update the mapping data based on the identified frame error rate.