US 12,445,151 B2
Error correcting code encoding circuit and semiconductor device including the same
Kijun Jeon, Suwon-si (KR); Kyoungbin Park, Suwon-si (KR); Hong Rak Son, Suwon-si (KR); Dae-Yeol Yang, Suwon-si (KR); Geunyeong Yu, Suwon-si (KR); Bohwan Jun, Suwon-si (KR); and Youngjun Hwang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 28, 2023, as Appl. No. 18/520,707.
Claims priority of application No. 10-2023-0045538 (KR), filed on Apr. 6, 2023.
Prior Publication US 2024/0340025 A1, Oct. 10, 2024
Int. Cl. H03M 13/11 (2006.01); H03M 13/00 (2006.01)
CPC H03M 13/1185 (2013.01) [H03M 13/1168 (2013.01); H03M 13/616 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An error correcting code (ECC) encoding circuit configured to encode a codeword based on a parity check matrix and to generate an encoded codeword (ECW) including an information bit and a parity bit,
wherein the ECC encoding circuit includes:
a parity check matrix (PCM) generator configured to generate the parity check matrix; and
an encoding unit coupled to the PCM generator and configured to generate the encoded codeword based on the codeword and the parity check matrix;
wherein the parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit, and
wherein the parity part includes:
a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure;
a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a being a natural number greater than or equal to 1;
a block matrix D composed of the first sub-matrix; and
a block matrix E including the first sub-matrix and a masked (1−(a+1))-th sub-matrix,
wherein the block matrix B and the block matrix D are positioned in the same sub-column,
wherein the block matrix T and the block matrix E are positioned in the same sub-column,
wherein a location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E,
wherein a location where the (1−a)-th sub-matrix is placed in the block matrix B precedes a location where the first sub-matrix is placed in the block matrix E,
wherein the first sub-matrix of each of the block matrices T, B, D and E is defined as a unit matrix having a size of Z×Z, Z being a natural number,
wherein the (1−a)-th sub-matrix is defined as a matrix obtained by performing a left-cyclic shift ‘a’ times on the first sub-matrix, and
wherein the masked (1−(a+1))-th sub-matrix is defined as a matrix in which a first row is masked in a matrix obtained by performing a left-cyclic shift “a+1” times on the first sub-matrix.