| CPC H03M 1/785 (2013.01) [H02M 1/08 (2013.01); H03M 1/00 (2013.01); H03M 1/06 (2013.01); H03M 1/747 (2013.01)] | 20 Claims |

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1. An integrated circuit (IC) comprising:
a first resistor having a first terminal and a second terminal and having resistance R1;
N p-channel field-effect transistors (ladder PFETS) coupled together as a p-ladder, each ladder PFET having a source, a drain, and a gate, in which N is an integer greater than or equal to one, wherein if N is greater than one the ladder PFETS are coupled together as a p-ladder, so that the gates of the ladder PFETS are coupled together, the drains and sources of the ladder PFETS are cascade-coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor;
a differential amplifier including a first input, a second input, and an output;
a second resistor including a first terminal and a second terminal and having resistance y×R1, in which y is an integer greater than one, and a first terminal of the second resistor is coupled to the second terminal of the first resistor and the first input of the differential amplifier; and
y×N n-channel field-effect transistors (ladder NFETS) coupled together as an n-ladder, each ladder NFET having a source, a drain, and a gate, the gates of the ladder NFETS coupled together, the drains and sources of the ladder NFETS cascade-coupled between a first end and a second end of the n-ladder, the first end of the n-ladder coupled to the second terminal of the second resistor, and the second end of the n-ladder coupled to the output of the differential amplifier.
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