US 12,445,144 B2
Continuous-time ADC calibration techniques
Asha Ganesan, Markham (CA); Donald W. Paterson, Winchester, MA (US); Sharvil Pradeep Patil, Toronto (CA); and Nevena Rakuljic, Del Mar, CA (US)
Assigned to Analog Devices International Unlimited Company, Limerick (IE)
Filed by Analog Devices International Unlimited Company, Limerick (IE)
Filed on Apr. 26, 2023, as Appl. No. 18/139,779.
Prior Publication US 2024/0364356 A1, Oct. 31, 2024
Int. Cl. H03M 1/00 (2006.01); H03M 1/10 (2006.01); H03M 1/20 (2006.01); H03M 1/50 (2006.01); H03M 1/66 (2006.01)
CPC H03M 1/50 (2013.01) [H03M 1/1009 (2013.01); H03M 1/201 (2013.01); H03M 1/662 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A continuous-time (CT) analog-to-digital converter (ADC), comprising:
a delay circuit configured to generate a delay circuit output signal by applying a delay to an analog input signal;
a sub-ADC circuit configured to generate a sub-ADC circuit output signal based on the analog input signal;
a first sub-DAC circuit coupled to receive the sub-ADC circuit output signal and generate an analog representation of the sub-ADC circuit output signal, wherein the analog representation of the sub-ADC circuit output signal is combined with the delay circuit output signal to generate a residue signal;
an error estimation circuit configured to receive an ADC output signal and generate an error estimation circuit signal;
an error correction circuit configured to receive the error estimation circuit signal and generate a digital error-correction signal; and
an output node coupled to an input of the error estimation circuit and configured to generate the ADC output signal using: 1) the residue signal, 2) the sub-ADC circuit output signal, and 3) the digital error-correction signal.