US 12,445,142 B2
Channel circuit with asynchronous sampling from an oversampled analog-to-digital converter
Richard Galbraith, Rochester, MN (US); Michael J. Ross, Rochester, MN (US); Weldon M. Hanson, Rochester, MN (US); John T. Contreras, Palo Alto, CA (US); Iouri Oboukhov, Rochester, MN (US); Niranjay Ravindran, Rochester, MN (US); Pradhan Bellam, Rochester, MN (US); and Derrick E. Burton, Ladera Rach, CA (US)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 18, 2023, as Appl. No. 18/354,138.
Claims priority of provisional application 63/407,297, filed on Sep. 16, 2022.
Prior Publication US 2024/0097696 A1, Mar. 21, 2024
Int. Cl. H03M 1/12 (2006.01); H03M 1/06 (2006.01); H03M 1/20 (2006.01)
CPC H03M 1/207 (2013.01) [H03M 1/0629 (2013.01); H03M 1/1245 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A channel circuit, comprising:
an analog-to-digital converter configured with a sample rate that is an integer multiple of a baud rate of the channel circuit to generate an oversampled digital signal from an analog data signal;
a digital sample interpolator configured to:
receive the oversampled digital signal;
interpolate multiple digital sample values from the oversampled digital signal to determine interpolated digital signal values; and
output a baud rate digital signal comprised of interpolated digital signal values selected at the baud rate of the channel circuit; and
an iterative detector configured to detect data bits from the baud rate digital signal.