US 12,445,141 B2
Voltage-to-delay converter
Sai Vikas Kandimalla, Nalgonda (IN); Neeraj Shrivastava, Bangalore (IN); Visvesvaraya Appala Pentakota, Bangalore (IN); and Keshav Tiwari, New Delhi (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Oct. 31, 2023, as Appl. No. 18/498,358.
Prior Publication US 2025/0141460 A1, May 1, 2025
Int. Cl. H03M 1/12 (2006.01); G04F 10/00 (2006.01)
CPC H03M 1/12 (2013.01) [G04F 10/005 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A voltage-to-delay converter circuit comprising:
a first reset transistor having a first terminal coupled to a power supply terminal, and having a gate terminal coupled to receive a reset signal;
a first integrating capacitor having a first terminal coupled to a second terminal of the first reset transistor and having a second terminal;
a second reset transistor having a first terminal coupled to the power supply terminal, and having a gate terminal coupled to receive the reset signal;
a second integrating capacitor having a first terminal coupled to a second terminal of the second reset transistor and having a second terminal;
a first current source having a first terminal coupled to a common potential;
a first input transistor having a first terminal coupled to a second terminal of the first current source, a second terminal coupled to the first terminal of the first integrating capacitor, and a gate terminal coupled to receive a first input voltage;
a second input transistor having a first terminal coupled to the second terminal of the first current source, a second terminal coupled to the first terminal of the second integrating capacitor, and a gate terminal coupled to receive a second input voltage;
a discharge current source having a first terminal coupled to a second terminal of each of the first and second integrating capacitors, and a second terminal coupled to the common potential; and
a pulse generator having a first input coupled to the first terminal of the first integrating capacitor, a second input coupled to the first terminal of the second integrating capacitor, and first and second outputs.