| CPC H03L 7/093 (2013.01) [H04L 7/0016 (2013.01)] | 6 Claims |
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1. A timing recovery apparatus comprising: a timing error detection module and a loop filter;
wherein the timing error detection module is configured to determine N first signals, and input the N first signals to N input terminals of the loop filter; wherein each of the N first signals is a timing error message, and N is any integer greater than or equal to 2;
wherein the loop filter comprises: the N input terminals, a source filter, a first gain processing module, and a second gain processing module;
the N input terminals are configured to receive the N first signals;
the source filter comprises: an integral signal terminal and an addition terminal;
the first gain processing module is configured to perform first gain processing on the N first signals to obtain a second signal, and output the second signal to the addition terminal;
the second gain processing module is configured to perform second gain processing on the N first signals to obtain a third signal, and output the third signal to the integral signal terminal; and
the source filter is configured to integrate the third signal received by the integral signal terminal to obtain a fourth signal, and obtain a fifth signal according to the fourth signal and the second signal received by the addition terminal;
wherein the first gain processing module comprises: N first multipliers and a first adder; and the second gain processing module comprises: N second multipliers and a second adder,
wherein for each j in [1 . . . N], a jth first multiplier of the N first multipliers is configured to multiply a jth first signal of the N first signals by a jth gain parameter to obtain a jth sixth signal; a jth second multiplier of the N second multipliers is configured to multiply the jth first signal of the N first signals by a (j+N)th gain parameter to obtain a jth seventh signal,
wherein the first adder is configured to add up N sixth signals obtained by the N first multipliers to obtain the second signal,
wherein the second adder is configured to add up N seventh signals obtained by the N second multipliers to obtain the third signal,
wherein the timing error detection module comprises: N timing error detection units, wherein an ith timing error detection unit of the N timing error detection units is configured to determine an ith first signal; where i is any integer greater than or equal to 1 and less than or equal to N, and
wherein the ith timing error detection unit comprises: an ith timing error detector, a target measurement circuit, a first switch, a second switch and a first subtracter, wherein
the ith timing error detector is configured to determine an ith original first signal;
the target measurement circuit is configured to measure a mean value of the ith original first signal;
the first switch has one end connected to an output of the ith timing error detector, and the other end connected to an input of the target measurement circuit, and the first switch is configured to control on/off between the output of the ith timing error detector and the input of the target measurement circuit;
the second switch has one end connected to an output of the target measurement circuit, and the other end connected to an input of the first subtracter, and the second switch is configured to control on/off between the output of the target measurement circuit and the input of the first subtracter; and
the first subtracter is configured to subtract the mean value from the ith original first signal to obtain the ith first signal.
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