US 12,445,135 B2
Circuit, chip and semiconductor device
Chao Chieh Li, Hsinchu (TW); Chia-Chun Liao, Taipei (TW); Min-Shueh Yuan, Taipei (TW); and Chih-Hsien Chang, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on May 20, 2024, as Appl. No. 18/668,282.
Application 18/668,282 is a continuation of application No. 18/062,591, filed on Dec. 7, 2022, granted, now 12,021,537.
Application 18/062,591 is a continuation of application No. 16/573,853, filed on Sep. 17, 2019, granted, now 11,533,056, issued on Dec. 20, 2022.
Prior Publication US 2024/0305301 A1, Sep. 12, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03L 7/08 (2006.01); G01R 31/317 (2006.01); G04F 10/00 (2006.01); H03L 7/00 (2006.01)
CPC H03L 7/08 (2013.01) [G01R 31/31707 (2013.01); G01R 31/31711 (2013.01); G04F 10/005 (2013.01); H03L 7/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a time-to-digital converter (TDC), configured to receive a first signal having an identification and a first frequency, and output a digital signal associated with the identification of the first signal; and
an evaluation circuit, coupled to the TDC and coupled to a phase-locked loop (PLL) external to the circuit, the evaluation circuit being configured to evaluate the identification of the first signal based on a transition between a first voltage level and a second voltage level of the digital signal.