US 12,445,132 B2
Cryptographic hardware sharing systems and methods
Tim Vogt, San Jose, CA (US); Mark Everhard, San Jose, CA (US); and Narasimhakumar Mangipudi, Portland, OR (US)
Assigned to Lattice Semiconductor Corporation, Hillsboro, OR (US)
Filed by Lattice Semiconductor Corporation, Hillsboro, OR (US)
Filed on Nov. 30, 2023, as Appl. No. 18/525,388.
Claims priority of provisional application 63/429,777, filed on Dec. 2, 2022.
Prior Publication US 2024/0187001 A1, Jun. 6, 2024
Int. Cl. H03K 19/17768 (2020.01); H03K 19/173 (2006.01)
CPC H03K 19/17768 (2013.01) [H03K 19/1737 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A programmable logic device (PLD) comprising:
a configuration engine configured to provide configuration data for processing using a first set of security functions;
a PLD fabric comprising an array of memory cells configured to operate upon being programmed based on the configuration data and configured to provide user data for processing using a second set of security functions; and
a security engine comprising:
a cryptographic circuit; and
an interface integration logic circuit configured to selectively couple, based on a security engine control indicator, the configuration engine to the cryptographic circuit or the PLD fabric to the cryptographic circuit, wherein the cryptographic circuit is configured to perform the first set of security functions for the configuration engine when coupled to the configuration engine by the interface integration logic circuit and/or the second set of security functions for the PLD fabric when coupled to the PLD fabric by the interface integration logic circuit.