| CPC H03K 19/00361 (2013.01) [H03K 17/102 (2013.01); H03K 19/018521 (2013.01)] | 23 Claims |
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1. A bidirectional I/O circuit comprising:
a bidirectional pad configured to receive and transmit signals;
an output post driver configured to control an output signal of the bidirectional pad during a normal mode;
a floating N-well network configured to apply a VDD-level bias to the output post driver based on an input signal of the bidirectional pad during a power down mode;
a post driver control circuit configured to set an input voltage level of the output post driver to a VDD level during the power down mode to prevent a leakage current path from being formed through the output post driver; and
an ESD protection circuit disposed on an input side of the bidirectional pad to protect a component included in the bidirectional I/O circuit,
wherein the output post driver comprises a first PMOS transistor having a source connected to VDD, a drain connected to the bidirectional pad, and a gate connected to the post driver control circuit,
wherein a parasitic diode is formed between the drain of the first PMOS transistor and an N-well of the first PMOS transistor,
wherein an N-well node of the first PMOS transistor is connected to the floating N-well network without being connected to the source of the first PMOS transistor,
wherein the ESD protection circuit comprises a PMOS transistor having a source connected to the VDD, a drain connected to the input side of the bidirectional pad, and a gate connected to the floating N-well network,
wherein a parasitic diode is formed between the drain of the PMOS transistor and an N-well node of the PMOS transistor, and
wherein the N-well node of the PMOS transistor is connected to the floating N-well network without being connected to the source of the PMOS transistor.
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