US 12,445,130 B2
Output buffer circuit and semiconductor device
Hiroshi Tsuchi, Yokohama (JP)
Assigned to LAPIS Technology Co., Ltd., Yokohama (JP)
Filed by LAPIS Technology Co., Ltd., Yokohama (JP)
Filed on Sep. 19, 2023, as Appl. No. 18/470,368.
Claims priority of application No. 2022-156313 (JP), filed on Sep. 29, 2022.
Prior Publication US 2024/0113712 A1, Apr. 4, 2024
Int. Cl. H03K 19/003 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01)
CPC H03K 19/00315 (2013.01) [H03K 19/0013 (2013.01); H03K 19/018521 (2013.01)] 8 Claims
OG exemplary drawing
 
1. An output buffer circuit, outputting an output signal obtained by amplifying an input signal from an output terminal, comprising:
a bias circuit, generating a first bias voltage and a second bias voltage;
a first conductivity type first transistor, receiving the input signal by a gate and supplying a first power source voltage to a first node in response to an ON state according to the input signal;
a second conductivity type second transistor, receiving the input signal by a gate and supplying a second power source voltage to a second node in response to the ON state according to the input signal;
a second conductivity type third transistor, receiving the first bias voltage by a gate, with a source connected to the second node and a drain connected to the first node;
a first conductivity type fourth transistor, receiving the second bias voltage by a gate, with a source connected to the first node and a drain connected to the second node;
a first conductivity type fifth transistor, receiving a voltage at the first node by a gate and supplying the first power source voltage to the output terminal in response to the ON state according to the voltage at the first node; and
a second conductivity type sixth transistor, receiving a voltage at the second node by a gate and supplying the second power source voltage to the output terminal in response to the ON state according to the voltage at the second node.