US 12,445,124 B2
Voltage aware bias receiver in an analog node
Abhinav Murali, Bangalore (IN); and Pradeep Kumar Sana, Bangalore (IN)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 26, 2024, as Appl. No. 18/587,145.
Prior Publication US 2025/0274118 A1, Aug. 28, 2025
Int. Cl. H03K 17/30 (2006.01); H03K 17/10 (2006.01); H03K 17/687 (2006.01)
CPC H03K 17/302 (2013.01) [H03K 17/102 (2013.01); H03K 17/6872 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an input node;
a bias receiver; and
a protection device, a gate of the protection device coupled to the bias receiver, the bias receiver tied to a lower voltage domain level, a first source or drain of the protection device coupled to the input node to receive a current from an analog node or a higher voltage domain level from the analog node and a second drain or source of the protection device coupled to a current output node, when the current is received through the input node to the protection device and the lower voltage domain level is in a non-collapse mode, configured to pass the current through the protection device to the current output node.