US 12,445,120 B2
Dynamic setup and hold times adjustment for memories
John J. Wuu, Fort Collins, CO (US); Jaroslaw Kuszczak, Markham (CA); and Gaurav Singla, Markham (CA)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Dec. 29, 2021, as Appl. No. 17/564,747.
Claims priority of provisional application 63/254,873, filed on Oct. 12, 2021.
Prior Publication US 2023/0112432 A1, Apr. 13, 2023
Int. Cl. H03K 5/159 (2006.01)
CPC H03K 5/159 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a sequential circuit;
control circuitry; and
a signal arrival adjuster; and
wherein the control circuitry is configured to:
receive indications of one or more operating conditions utilized by at least the sequential circuit of the apparatus that cause a change in latencies of signals of the apparatus; and
generate a control signal based on detection of a combination of the one or more operating conditions; and
wherein the signal arrival adjuster comprises circuitry configured to:
receive a first signal that is one of an input clock signal and an input data signal; and
convey, to the sequential circuit, one of a first version of the first signal or a second version of the first signal, based on the control signal, wherein the second version of the first signal is delayed with respect to the first version of the first signal.