US 12,445,119 B2
Tuning of data interface timing between clock domains
Eeshan Miglani, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Nov. 30, 2023, as Appl. No. 18/524,925.
Prior Publication US 2025/0183882 A1, Jun. 5, 2025
Int. Cl. H03K 5/14 (2014.01); H03K 3/356 (2006.01); H03K 5/15 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/14 (2013.01) [H03K 3/356043 (2013.01); H03K 5/15093 (2013.01); H03K 2005/00267 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a clock delay driver having a clock input receiving an input clock signal, a first output presenting an output domain clock signal having a selected delay relative to the input clock signal, a second output presenting an early clock signal leading the output domain clock signal by a selected interval, and a third output presenting a late clock signal lagging the output domain clock signal by a selected interval;
a latch having a data input, a clock input coupled to the first output of the clock delay driver, and a data output;
a timing error detection circuit having a first input receiving an input domain clock signal, a second input coupled to the second output of the clock delay driver, a third input coupled to the third output of the clock delay driver, and an error flag output presenting early and late fail flags responsive to detecting timing errors of the early and late clock signals, respectively, relative to the input domain clock signal; and
timing loop circuitry having an input coupled to the error flag output of the timing error detection circuit, and an output coupled to a control input of the clock delay driver.