US 12,445,117 B2
Dynamic phase adjustment for high speed clock signals
Madusudanan Srinivasan Gopalan, Issaquah, WA (US); Christopher Schell, Tacoma, WA (US); and Benyong Zhang, Auburn, WA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Sep. 13, 2023, as Appl. No. 18/367,911.
Application 18/367,911 is a continuation of application No. 17/853,085, filed on Jun. 29, 2022, granted, now 11,799,460.
Prior Publication US 2024/0007091 A1, Jan. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 5/01 (2006.01); G06F 1/12 (2006.01); H03K 3/037 (2006.01); H03K 21/02 (2006.01); H03K 5/00 (2006.01)
CPC H03K 5/01 (2013.01) [G06F 1/12 (2013.01); H03K 3/037 (2013.01); H03K 21/02 (2013.01); H03K 2005/00058 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A circuit comprising:
clock divider circuitry having a first control input and a first output, and including frequency divider circuitry configured to apply a divide ratio to a reference clock to provide a first clock signal at the first output;
a digital delay circuitry having an input coupled to the first output, and having a second control input and a second output;
an analog delay circuitry having an input coupled to the second output, and having a third control input and a clock output; and
control circuitry having outputs coupled to the first, second, and third control inputs, the control circuitry configured, responsive to an indication to provide an adjusted output clock signal at the clock output, to:
control the frequency divider circuitry to adjust the divide ratio applied to the reference clock to provide the first clock signal;
control the digital delay circuitry to delay the first clock signal to provide a second clock signal; and
control the analog delay circuitry to delay the second clock signal to provide the adjusted output clock signal.