US 12,445,114 B1
Intelligent power noise reduction
Jason Miller, Stamford, CT (US); and Sivaseetharaman Pandi, Round Rock, TX (US)
Assigned to Amazon Technologies, Inc., Seattle, WA (US)
Filed by Amazon Technologies, Inc., Seattle, WA (US)
Filed on Sep. 6, 2023, as Appl. No. 18/462,167.
Int. Cl. G06F 1/28 (2006.01); G06N 3/08 (2023.01); H03H 11/04 (2006.01)
CPC H03H 11/04 (2013.01) [G06F 1/28 (2013.01); G06N 3/08 (2013.01); H03H 2011/0488 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for performing power noise reduction for an integrated circuit device, the method comprising:
executing a plurality of workloads on the integrated circuit device;
for each of the plurality of workloads, optimizing configuration of a power distribution network having active filtering components to meet a voltage noise target and a bit error rate target to derive a filtering configuration;
selecting the filtering configuration for a highest power consumption workload of the plurality of workloads to use as a preset configuration of the power distribution network for the plurality of workloads; and
subsequent to deriving the preset configuration of the power distribution network:
executing a workload that belongs to the plurality of workloads on the integrated circuit device;
applying the preset configuration of the power distribution network for the workload being executed;
monitoring a voltage noise level and a bit error rate of the integrated circuit device; and
dynamically adjusting the power distribution network and operating conditions for the workload to keep the integrated circuit device within the voltage noise target and the bit error rate target.