| CPC H03H 9/2457 (2013.01) [B81C 1/0069 (2013.01); H03H 3/0072 (2013.01); H03H 3/0076 (2013.01); H03H 9/1057 (2013.01); B81C 2201/0164 (2013.01); B81C 2201/0171 (2013.01)] | 22 Claims |

|
1. A semiconductor device comprising:
a substrate;
a layer stack on the substrate, the layer stack including a lid layer, the lid layer having been conformally deposited over one or more underlying layers of the layer stack, the lid layer having at least one vent, the at least one vent being plugged so as to, in combination with the lid layer, hermetically seal a cavity relative to the substrate, the cavity being defined by etch of one or more oxide layers of the layer stack through the at least one vent prior to the at least one vent being plugged; and
a microelectromechanical system (MEMS) device having a body that is free to vibrate or deflect within the cavity during operation of the semiconductor device, the body formed from one or more layers fabricated from the substrate, wherein at least one layer of the one or more layers has a phosphorus dopant concentration greater than or equal to 1019/cm3;
wherein the semiconductor device comprises circuitry to (1) receive a signal representing a temperature of operation and a signal representing the resonance frequency, and (2) generate, using the signal representing the temperature of operation and the signal representing the resonance frequency, a timing reference signal, wherein the timing reference signal is to have a reduced proportional variation in frequency relative to a proportional variation in the resonance frequency as a function of change in the temperature of operation of the resonator.
|