| CPC H03B 5/36 (2013.01) [H03H 9/178 (2013.01); H03H 9/2426 (2013.01); H10D 30/62 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01); H03L 7/099 (2013.01)] | 25 Claims |
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1. An apparatus comprising:
a first transistor comprising a source region, a drain region, a channel region between the source and drain regions, a gate contact, and a dielectric between the gate contact and the channel region, wherein the channel region of the first transistor is in a first well;
a second transistor comprising a source region, a drain region, a channel region between the source and drain regions, a gate contact, and a dielectric between the gate contact and the channel region, wherein the channel region of the second transistor is in a second well of opposite polarity than the first well;
a third transistor comprising a source region, a drain region, a channel region between the source and drain regions, a gate contact, and a dielectric between the gate contact and the channel region, wherein the channel region is in a third well of the same polarity as the first well;
a first direct current (DC) contact to receive DC current, the first DC contact coupled to the gate contact of the first transistor, to the gate contact of the second transistor, and to the gate contact of the third transistor;
a second direct current (DC) contact to receive DC current, the second DC contact coupled to the drain region of the second transistor; and
alternating current (AC) contacts to receive AC current, the AC contacts coupled to the source and drain regions of the first transistor and the third transistor.
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