| CPC H02M 3/1586 (2021.05) [H02M 1/08 (2013.01); H02M 1/14 (2013.01)] | 20 Claims |

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1. An apparatus comprising:
a first stacked transistor voltage converter circuit;
a first stacked transistor driver circuit coupled to the first stacked transistor voltage converter circuit, the first stacked transistor driver circuit to receive a first voltage transition input signal;
a second stacked transistor voltage converter circuit coupled to the first stacked transistor voltage converter circuit; and
a second stacked transistor driver circuit coupled to the second stacked transistor voltage converter circuit, the second stacked transistor driver circuit to receive a second voltage transition input signal;
wherein the first stacked transistor voltage converter circuit and the second stacked transistor voltage converter circuit are configured to change a voltage output signal at a first upper drain node of the first stacked transistor voltage converter circuit from a first logical state to a second logical state responsive to the first voltage transition input signal and the second voltage transition input signal.
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